Di Huang

Associate Professor

ICT, CAS

Research Interests

Automated Chip Design

Program Synthesis and Code Generation

Large Language Models

About

I am an Associate Professor at Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS). I received my B.S. in Physics from Tsinghua University and my Ph.D. from ICT, CAS. My research focuses on automated chip design and code generation, with particular interest in systematically training chip design foundation models and building practical chip design systems powered by these models. I am also broadly interested in Embodied AI.

I am the lead contributor to the CodeV series, a family of fully open-source foundation models for HDL (e.g., Verilog) generation.

Feel free to reach me at huangdi[AT]ict.ac.cn.

News

2025-11

4 papers were accepted to AAAI 2026 (2 oral) 🎉

2025-10

2 papers were accepted to IEEE TCAD 🎉

2025-09

We have open-sourced our HDL generation foundation models CodeV series on 🤗Hugging Face, along with their datasets🔥🔥🔥

2025-09

4 papers were accepted to NeurIPS 2025 (1 spotlight) 🎉

Selected Publications

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StepFun-Formalizer: Unlocking the Autoformalization Potential of LLMs through Knowledge-Reasoning Fusion

Yutong Wu, Di Huang, Ruosi Wan, Yue Peng, Shijie Shang, Chenrui Cao, Lei Qi, Rui Zhang, Zidong Du, Jie Yan, Xing Hu

AAAI 2026 Oral

Paper Model

AGON: Automated Design Framework for Customizing Processors from ISA Documents

Chongxiao Li, Di Huang, Pengwei Jin, Tianyun Ma, Husheng Han, Shuyao Cheng, Yifan Hao, Yongwei Zhao, Guanglin Xu, Zidong Du, Rui Zhang, Xiaqing Li, Yuanbo Wen, Xing Hu, Qi Guo

IEEE TCAD 2025

Paper

MigGPT: Harnessing Large Language Models for Automated Migration of Out-of-Tree Linux Kernel Patches Across Versions

Pucheng Dang, Di Huang, Dong Li, Kang Chen, Yuanbo Wen, Qi Guo, Xing Hu

NeurIPS 2025 Spotlight

Paper

CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization

Yang Zhao, Di Huang, Chongxiao Li, Pengwei Jin, Muxin Song, Yinan Xu, Ziyuan Nan, Mingju Gao, Tianyun Ma, Lei Qi, Yansong Pan, Zhenxing Zhang, Rui Zhang, Xishan Zhang, Zidong Du, Xing Hu

IEEE TCAD 2025

Project Page Paper Code Data Model

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

Pengwei Jin, Di Huang, Chongxiao Li, Shuyao Cheng, Yang Zhao, Xinyao Zheng, Jiaguo Zhu, Shuyi Xing, Bohan Dou, Rui Zhang, Zidong Du, Xing Hu

Preprint

Paper Code Data

QiMeng-CodeV-R1: Reasoning-Enhanced Verilog Generation

Yaoyu Zhu, Di Huang, Hanqi Lyu, Xiaoyun Zhang, Chongxiao Li, Wenxuan Shi, Yutong Wu, Jianan Mu, Jinghua Wang, Pengwei Jin, Shuyao Cheng, Shengwen Liang, Xishan Zhang, Rui Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen